Hardware Design Engineer - Graphics Silicon Implementation

Job TitleEngineer, Adreno Graphics CoresCompanyQualcomm Technologies, Inc.Job AreaEngineering Group, Engineering Group > GPU ASICS EngineeringQualcomm CDMA Technologies, is the world leader in wireless ICs powering the majority of 3G & 4G devices and the largest fabless semiconductor company in the world. The Graphics team is looking for an Engineer to work on QUALCOMMs Adreno Graphics cores in the area of implementation and methodology. The successful candidate will work in Adreno GPU team and will be responsible for various functions from RTL integration through to physical design.As a member of the Graphics team, the successful applicant will help integrate, implement and develop state of the art GPU cores and will be working closely with the graphics microarchitecture and physical design teams.

The successful candidate will possess basic understanding of RTL design and ASIC design flow from RTL to GDS2 such as synthesis, static timing analysis, formal verification, physical design and ECO generation and verification.Knowledge and experience in the following is a definite advantage:Verilog and System-Verilog languagesRTL integration, partitioning, transformation, and analysis.Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock domain crossing checks.Package, qualify and deliver FE design collateral.Develop innovative methods to improve front-end design integration process.Collaborate effectively with Architecture, Design, DV, SOC, DFT, and IMPL teams spanning multiple sites.Version control systemsRTL synthesis using physically aware toolsFormal Verification using industry standard tools for RTL-netlist and netlist-netlist checksECO methods for functional and timing fixesManaging design goals in power, performance and areaMinimum Skills:0-5 years relevant industry experienceDigital design and RTL development understanding using Verilog and/or System VerilogBasic level knowledge of synthesis, static timing, timing closure, constraints and formal verificationExposure to Synopsys Design Compiler tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTimePreferred Skills:Experience with UNIX, Perl, TCL or shell scriptingAbility to analyze architectural and micro architectural details to drive design partitioning.Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA.Excellent interpersonal and analytical skills as well as ability to work independentlyHighly motivated, excellent team spirit, obsession with deliverable quality and customer orientedMinimum Qualifications:• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.Pay range and Other Compensation & Benefits :$161,800.00 - $242,600.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted.

Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.