ByteDance is seeking an ASIC Design Engineer to build industry-leading video codec hardware IPs (FPGA/ASIC) for high-performance video processing. You will work with architecture, algorithms, software, firmware, and verification teams on scalable, low-power designs.
The role requires strong RTL design experience, HDL proficiency, and Python scripting. A Bachelor's in CS/EE and knowledge of video codecs are essential. On-site in San Jose with regular employment type.
#J-18808-Ljbffr