Full-Chip Timing Design & Modeling Engineer

Altera is seeking a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and perform full-chip timing for next-generation FPGA products. You will collaborate with cross-functional teams to define timing modeling strategies, generate high-level timing models, and validate timing models across multi-site teams.

The role requires hands-on STA experience, design automation scripting in Python and Tcl, and deep knowledge of LVF/POCV concepts, timing constraints, and