Full-Chip Static Timing Engineer — Equity + Bonus

Google LLC in Mountain View, CA seeks a Static Timing Analysis Engineer to own full-chip timing closure for SoCs and define timing signoff processes. You will enforce constraints, derates, and signoff criteria across the chip flow. In-person interviews are typically required.

Ideal candidates have experience with PrimeTime/Tempus, ASIC timing flows, and scripting for automation. Collaboration with design teams will drive robust timing solutions for Google's hardware products.