Cadence is seeking an experienced Front End Design lead in the Austin area to guide RTL engineers and drive IP/SOC integration. You will oversee pre-silicon verification and collaborate with DV, PD, and firmware teams to ensure on-time delivery.
The role emphasizes technical leadership, microarchitectural feature development, and hands-on RTL/synthesis activities to meet aggressive PPA goals. Cadence offers an inclusive, innovation-driven environment.
#J-18808-LjbffrFront End Design Engineering Director in austin at Unknown Company
This position is listed as full time and onsite.