FPGA Soft CPU Architect – RISC-V/Nios V

Altera is seeking an innovative Soft CPU Design Engineer to join its IP Engineering team at the San Jose, CA headquarters. You will design and optimize Soft CPU cores tailored for Altera FPGA architectures, focusing on high performance and area efficiency.

Responsibilities include RTL design in SystemVerilog, PPA optimization, timing closure, configurable ISA extensions, and collaboration with DV teams on simulations and hardware validation.