FPGA Engineering Manager - Memory Test & RTL Lead

Teradyne's Memory Test Division in Tualatin, OR is seeking an experienced FPGA Engineering Manager to lead a small team and deliver advanced memory test solutions, combining digital and analog design with PCIe, DDR, and SERDES interfaces.

You will plan multiple FPGA projects, mentor 4–6 engineers, collaborate across hardware, software, and firmware, and drive architectural reviews, RTL coding, and lab validation to ensure on-time delivery.