FPGA/ASIC Methodology Engineer: Drive Design & Validation

Teradyne in North Reading, MA seeks an ASIC/FPGA Methodology Engineer to define, develop, and maintain FPGA/ASIC design and verification workflows. Strong background in FPGA/embedded design and Linux-based tooling is essential for this role.

The candidate will optimize design flows for Vivado/Quartus, collaborate with design and verification teams, and contribute to CI/CD implementation using Jenkins, Docker, and Git. Excellent problem-solving and teamwork are required.