FPGA/ASIC Hardware Engineer Internship

Hudson River Trading (HRT) invites you to join its Hardware Engineering Internship, where you will create hardware in SystemVerilog and develop verification environments in Python. You’ll work on cutting-edge FPGA/ASIC technology in a fast-paced, finance-focused setting.

Expect independent projects, early immersion in design and verification, and exposure to HRT’s research and trading infrastructure. Ideal for students graduating in 2028 with strong problem-solving skills.