FPGA/ASIC Design Engineer for SoC Systems

SpaceX is seeking an FPGA/ASIC Design Engineer to design and implement SoC blocks for Starlink. You will work across systems, firmware, and design teams to deliver cutting‑edge chips for space and ground hardware.

The role requires RTL design experience, proficiency in SystemVerilog/Verilog, and familiarity with HDL tools. A strong physics/engineering background and willingness to work extended hours are expected.