FPGA & ASIC Verification Engineer - SystemVerilog/UVM

Teradyne is seeking a Digital Logic Verification Engineer at our North Reading, MA center to focus on FPGA verification and related RTL work. You will collaborate with cross-functional teams to deliver robust designs, developing testbenches and UVM environments, and ensuring high coverage through systematic debugging and reviews.

The role requires 3+ years in digital logic verification, proficiency with SystemVerilog/UVM, and hands-on experience with Cadence Xcelium.