FPGA & ASIC Compute Test Design Manager

Teradyne North Reading is seeking an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/digital IP team. You will design and verify FPGA/ASIC components, collaborate with multiple engineering disciplines, and drive timely, high-quality deliverables for next-generation Compute Test products.

You will oversee staffing, planning, and budget, contribute to RTL code, and mentor engineers while coordinating with cross-functional teams to meet product requirements.