At Cadence, We Hire And Develop Leaders And Innovators Who Want To Make An Impact On The World Of TechnologyBe Part Of The Cadence DDR PHY IP Front End Design Team Responsible For:Develop firmware for DDR5 PHY using microcontrollersDeveloping firmware in C typically involving bare-metal programming and developing low-level APIs on microcontrollers.Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.Develop and debug firmware in RTL based hardware simulations (C + Verilog simulations)Develop and debug on silicon bring-up boards.Required Skills:Good knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.Relevant experience in developing bare-metal firmware for high-speed SerDes or memory interface physical layer blocks.Good knowledge of C programming language for embedded software development and use of relevant IDE.Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.Good knowledge of shell/Perl/Python/TCL scriptingGood experience on verification EDA tools like simulators and waveform viewersWe're Doing Work That Matters. Help Us Solve What Others Can't.