• Strong Verilog HDL and RTL design expertise.
• Good knowledge of CDC, reset design, pipelining, FIFO/memory, and synchronization.
• Experience with FPGA tools like Vivado, Quartus, Libero, Questa/ModelSim.
• Strong understanding of STA, timing constraints, timing closure, and clock architecture.
• Hands-on experience in FPGA hardware bring-up and debugging
Field-Programmable Gate Arrays Engineer in Raleigh at Sira Consulting, an Inc 5000 company
This position is listed as full time and onsite. It was posted 2 days ago.
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