Apple is seeking an experienced SoC physical design engineer in the United States to drive the full physical design flow from netlist to tape-out. You will coordinate with design and verification teams to deliver high-performance silicon, handling floorplanning, clock and power planning, and hard-IP tight integration.
Responsibilities include managing voltage/clock domain issues, ESD, and power distribution while guiding layout rule checks, timing, and real-time process monitoring for
#J-18808-Ljbffr