Intel is seeking an Entry Level Design Verification Engineer for the Silicon Chassis team to contribute to the verification of interconnect and chassis IPs underpinning Intel's SoC and platform products.
You will work with senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures — developing end-to-end verification skills from day one. This college-grad role is on-site in Santa Clara, CA.
#J-18808-LjbffrEntry-Level Design Verification Engineer - AI-Driven HW Testing in santa clara at Unknown Company
This position is listed as full time and onsite.