Job-ID Reference PREFERRED EXPERIENCE: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) Strong proficiency in System Verilog Assertions (SVA) and formal property specification Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis Familiarity with scripting languages (TCL, Python, Perl) for flow automation Extensive experience in design verification with a strong focus on formal verification Expertise in System Verilog and UVM-based verification methodologies - Nice to have
Engineering - Verification Engineer 4 in austin at Unknown Company
This position is listed as full time and onsite.