DV Lead

CompetitiveCalifornia, United StatesSemiconductor PermanentA semiconductor startup based in Sunnyvale, CA is developing next-generation graphics processors focused on delivering exceptional performance and efficiency. The company embraces a first-principles engineering mindset and is motivated by a mission to make immersive content creation, simulation, and consumption more accessible to everyone. Its culture values bold thinking, adaptability, and collaborative problem-solving in pursuit of ambitious technical goals.The company is seeking a Principal Design Verification Engineer to lead verification strategy and execution across complex IPs and full-chip SoCs. This role involves building and mentoring a high-performing DV team, defining end-to-end verification methodologies from block to full-chip level, and driving coverage closure and signoff readiness.

Responsibilities include leading UVM-based verification environments, developing scalable testbench architectures, overseeing regression infrastructure, and managing advanced verification flows including GLS, low-power verification, formal verification, linting, and CDC/RDC analysis.Candidates should have a Bachelor’s or Master’s degree in Electrical Engineering or a related field, along with 12–15 years of ASIC/SoC verification experience and a proven record of leading teams through multiple tapeouts. Strong expertise in SystemVerilog, UVM, constrained-random verification, assertions (SVA), and debugging complex SoC-level issues is required, along with hands-on experience using tools such as Synopsys VCS, Cadence Xcelium, and Verdi. A deep understanding of CDC/RDC methodologies, low-power verification, gate-level simulation, and SDF annotation is also essential.Preferred qualifications include experience with CPU, GPU, AI, or networking SoCs, familiarity with emulation platforms such as Synopsys ZeBu, and experience supporting post-silicon validation and bring-up. Additional strengths include GLS debugging expertise, performance verification knowledge, and scripting skills in Python or Tcl for automation and regression scaling.

The role requires strong leadership, communication, and cross-functional collaboration skills, with close interaction across RTL, physical design, and post-silicon teams to ensure successful silicon delivery.