Director of Hardware Engineering – High-Speed IP & RTL

Baya Systems is seeking a Manager/Director of Hardware Engineering in Santa Clara, onsite only. You will lead a first-level team of RTL microarchitects and DV engineers, owning end-to-end interconnect IP from design to tape-out.

Requirements include 8+ years in ASIC/IP development with 2–3 years in leadership, strong SystemVerilog/Verilog skills, and expertise in high-speed protocols like PCIe/UCIe/CXL/Ethernet. A startup mindset and collaboration across disciplines are essential.