SK hynix America seeks a Director of Buffer & Memory Subsystem Architecture to lead HW/SW co-design for next-generation HBF-xPU systems in San Jose, CA. You will translate AI workload traces into architectural policies for caching, prefetching, and data movement, with a focus on memory controllers and performance modeling.
You will own architecture decisions, interface contracts, and system-level efficiency across hardware and software, driving latency and bandwidth improvements.
#J-18808-LjbffrDirector, Next-Gen Memory Subsystem Architecture in san jose at Unknown Company
This position is listed as contract and onsite.