Digital - Staff Digital Design Engineer - PHY

Eliyan Staff Digital Design EngineerJoin the leading chiplet startup! As an Eliyan Staff Digital Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the frontend design of our D2D PHY - the core tech behind NuLink, our chiplet interconnect platform.

You'll own the digital PHY from microarchitecture through synthesis, working closely with our architecture, analog, verification, and physical design teams. This is a hands-on technical leadership role. You'll define PHY architecture, write RTL, optimize for synthesis, create timing constraints, develop firmware sequences, and ensure clean integration across the stack.

Your work directly enables next-gen chiplet-based AI and HPC systems. We offer a fun work environment with excellent benefits. ONSITE M-F.Key Responsibilities:Architecture & RTL DesignOwn D2D PHY digital design from microarchitecture definition through synthesis and PD handoffDesign data path and clocking architecture for UCIe-compliant advanced package PHYWrite RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskewCreate microarchitecture specs with power analysis, latency metrics, and performance characterizationMake architectural trade-offs balancing performance, power, area, and timingSynthesis & OptimizationDrive synthesis optimization: area, timing, power, QoRCreate comprehensive SDC constraints for multi-clock domains, false paths, multi-cycle paths, CDCGenerate UPF power specifications with voltage domains, isolation, and retentionEstablish LINT/CDC flows with rulesets and waiver managementDeliver synthesis-ready netlists with handoff documentation for physical designTechnical Leadership & CollaborationCoordinate with analog PHY team on digital control for TX/RX, PLL, calibrationPartner with verification team on testbench requirements, coverage goals, and protocol complianceCollaborate with physical design on placement guidelines, clock tree requirements, routing constraintsWork with firmware team on register interfaces, link training sequences, runtime controlMentor 2-3 digital designers on frontend design and synthesis optimizationDrive design reviews and technical decisions across teamsRequired Qualifications:8+ years digital frontend design with 4+ years in PHY or high-speed interfaces3+ successful tapeouts as design lead in advanced nodes (7nm or below)Deep expertise in D2D PHY, DDR PHY, or SerDes digital designExpert SystemVerilog RTL design with strong synthesis optimization skillsStrong understanding of UCIe or other high-speed interfaces like DDR/SerdesAdvanced CDC design, link training protocols, elastic buffer architecturesHands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)Experience with SDC constraints, UPF, STA methodologyProven ability to lead frontend design and coordinate across teamsPreferred Qualifications:12+ years with demonstrated technical leadershipUCIe PHY design or certification experienceDDR4/DDR5/LPDDR PHY or DFI interface experienceSerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experienceAdvanced packaging knowledge: 2.5D, 3D, organic substrateFirmware development for PHY control or low-level driver implementationPython/Perl/Tcl scripting for design automationPublications or patents in PHY design