Digital IC Design Engineer InternFremont, California, United StatesWe are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.Team Description:The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.Job Description and Responsibilities:We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology.
The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern, your responsibilities will include:Micro-architecture design and RTL implementation of:Low-power digital signal processorsLow-power general-purpose hardware acceleratorsLow-power graphics processing unitsLow-power radio MAC/PHYLow-power serial link MAC/PHYDesign and implementation of hardware/software interface with firmware engineersApplication-specific architecture optimization including:Complex system modeling for energy and performance benchmarksWorkload analysis and modelingLeveraging architecture-level design trade-offs with process technology and workload typeBalancing energy efficiency and performance under manufacturing process variationComplex system-on-chip verificationBehavioral level modeling and model equivalence checkFPGA emulationAnalog mixed-signal co-simulationDesign for testabilityCollaboration on silicon bring-up tests with silicon validation engineersRequired Qualifications:Evidence of exceptional ability in electrical engineering, computer science, or computer engineering2+ years of experience in digital designProficient in SystemVerilog, C/C++, PythonExperience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard toolsExperience in designing digital signal processing pipelines, from algorithm to RTLPreferred Qualifications:Experience in architecture optimization with process technology customizationExperience in the verification of complex digital systems, using industry standard toolsExperience in the physical design of complex digital systems, using industry standard toolsExperience testing and debugging digital system-on-a-chipsFunctional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVMExperience automating tool flowsExperience with embedded designExperience in processor instruction set architecture designExperience in compiler back-end design and customizationExperience designing PCBs or writing firmware.Expected Compensation:The anticipated hourly rate for this position is listed below.California Hourly Flat Rate: $35/Hr USDWhat We Offer:Full-time employees are eligible for the following benefits listed below.An opportunity to change the world and work with some of the smartest and most talented experts from different fieldsGrowth potential; we rapidly advance team members who have an outsized impactExcellent medical, dental, and vision insurance through a PPO planPaid holidaysCommuter benefitsMeals providedEquity (RSUs) *Temporary Employees & Interns excluded401(k) plan *Interns initially excluded until they work 1,000 hoursParental leave *Temporary Employees & Interns excludedFlexible time off *Temporary Employees & Interns excluded