Digital IC Design EngineerAustin, Texas, United States; Fremont, California, United StatesAbout Neuralink:We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.Team Description:The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.Job Description & Responsibilities:Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces.
Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.Micro-architecture design and RTL implementation of:Low-power digital signal processorsLow-power general-purpose hardware acceleratorsLow-power graphics processing unitsLow-power radio MAC/PHYLow-power serial link MAC/PHYDesign and optimization of hardware/software interface with firmware engineersApplication-specific architecture optimization including:Complex system modeling for energy and performance benchmarksWorkload analysis and modelingEnergy/performance profiling and analysisLeveraging architecture-level design trade-offs with process technology and workload typeBalancing cost and performance under manufacturing process variationCollaboration on silicon bring-up tests with verification engineersRequired Qualifications:Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experienceEvidence of exceptional ability in electrical engineering, computer science, or computer engineering5+ years of experience in digital designExpertise in SystemVerilog, C/C++, PythonExperience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard toolsExperience in designing digital signal processing pipelines, from algorithm to RTLPreferred Qualifications:Experience in architecture optimization with process technology customizationExperience in the verification of complex digital systems, using industry standard toolsExperience in the physical design of complex digital systems, using industry standard toolsExperience testing and debugging digital system-on-a-chipsFunctional modeling experience and logic verification with SystemVerilog, SystemC/C++Experience automating tool flowsExperience with embedded designExperience in processor instruction set architecture designExperience in compiler back-end design and customizationExpected Compensation:The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees' success with the company's long-term growth.
As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.Base Salary Range:$116,000 - $233,800 USDWhat We Offer:Full-time employees are eligible for the following benefits listed below.An opportunity to change the world and work with some of the smartest and most talented experts from different fieldsGrowth potential; we rapidly advance team members who have an outsized impactExcellent medical, dental, and vision insurance through a PPO planPaid holidaysCommuter benefitsMeals providedEquity (RSUs) *Temporary Employees & Interns excluded401(k) plan *Interns initially excluded until they work 1,000 hoursParental leave *Temporary Employees & Interns excludedFlexible time off *Temporary Employees & Interns excluded