DFT Timing Engineer – Chip-Level Closure & Automation

NVIDIA is seeking a DFT-Timing Engineer in Santa Clara, CA to drive timing analysis and closure for DFT logic on NVIDIA chips at block, cluster, and full-chip levels. You will collaborate with PD, DFX, Clocks and other teams to develop timing-closure strategies and create timing constraints for custom DFT designs.

You will implement ECOs and continuously improve workflows through automation and standardization.