DFT Engineer (DFT)

Architect and implement scan, MBIST, boundary scan and ATPG flows that deliver high coverage and low DPPM.

Design for Test San Jose, CA / Austin, TX (USA)

Our DFT engineers define the test architecture for SoCs and chiplets, insert and verify DFT logic, generate production patterns and support silicon bring-up on ATE. You will work across RTL, synthesis, STA and PD teams to make test a first-class part of the design.

What you'll do

• Define DFT architecture, test modes and IO mux schemes for SoC and multi-die designs.


• Insert scan with compression, MBIST, LBIST and IEEE 1149.1/1687 boundary scan.


• Generate and validate ATPG patterns (stuck-at, transition, path delay) and meet coverage targets.


• Develop and validate test-mode constraints; support test-mode STA.


• Run DFT simulations (RTL and gate-level) and debug pattern mismatches.


• Translate patterns to ATE format and support bring-up and diagnostics.

What you bring

• Bachelor's or Master's in Electrical/Computer Engineering.


• Strong experience with Tessent, TestMAX/DFTMAX or Modus.


• Solid understanding of scan, compression, MBIST and JTAG.


• Experience with ATPG and pattern simulation.


• Working knowledge of STA for test modes.


• Scripting in Tcl, Perl or Python.

Nice to have

• Hierarchical DFT and chiplet/multi-die test experience.


• Yield analysis and silicon diagnostics.

Why I2Intech

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.