DFT Design Engineering Director

DFT Design Engineering DirectorSan Jose, California, United StatesAstera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.About the RoleWe are seeking an experienced Director of Design for Test (DFT) to lead our DFT engineering efforts for the Scorpio family of PCIe switch products. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale. This role requires deep expertise in advanced packaging technologies including 2.5D and 3D integration, as our products leverage cutting-edge multi-die architectures.Key ResponsibilitiesDFT Strategy & LeadershipDefine and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packagingLead and mentor a team of DFT engineers across multiple product development cyclesCollaborate with design, verification, packaging, and product engineering teams to optimize test coverage and manufacturing costEstablish DFT best practices, methodologies, and flows for complex multi-billion transistor designs in advanced packaging configurationsAdvanced Packaging DFT ArchitectureDevelop DFT strategies for 2.5D/3D heterogeneous integration architectures:Multi-die test access and coordination through silicon interposersThrough-Silicon Via (TSV) testing and characterizationDie-to-die interface testing and Known Good Die (KGD) strategiesChiplet-level DFT with system-level test integrationHybrid bonding and micro-bump interconnect testingArchitect test access mechanisms for:Inter-die communication channels and high-bandwidth interfacesHBM/DRAM interfaces in 2.5D configurationsPower delivery network testing across multiple diesThermal and reliability test structuresDefine pre-bond and post-bond test strategies:Individual die screening and KGD qualificationStack-level testing for 3D integrated circuitsPackage-level test optimization and cost reductionTechnical ExecutionArchitect and implement advanced DFT features including:Scan insertion, ATPG, and compression strategies for multi-die systemsMemory BIST (MBIST) for embedded SRAM and register filesLogic BIST (LBIST) for at-speed testingIEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) for die-level and package-level accessIEEE 1838 (3D-DFT) standards for 3D stacked die testHigh-speed SerDes BIST and loopback testing across die boundariesAnalog/mixed-signal test hooks and observabilityBuilt-in Self-Repair (BISR) for redundancy managementDrive fault coverage targets (>99% stuck-at, >95% transition) across all diesOptimize test time and ATE costs while maintaining quality metricsDefine and implement production test programs and diagnostic capabilities for packaged devicesCross-Functional CollaborationPartner with physical design and packaging teams to optimize DFT area, timing, and package routing impactWork with silicon validation teams to enable post-silicon debug and characterization of multi-die systemsCollaborate with manufacturing, assembly, and test engineering for seamless production rampInterface with OSAT partners, substrate vendors, and ATE vendorsCoordinate with design teams on die partitioning and test accessibility planningQuality & ReliabilityDefine test coverage metrics and quality goals for multi-die productsImplement diagnostic and failure analysis capabilities for complex packaging failuresSupport yield enhancement and defect reduction initiatives across die and packageEstablish field return analysis and root cause investigation processesDevelop screening strategies for infant mortality and reliability issuesRequired QualificationsEducation & ExperienceMS or PhD in Electrical Engineering, Computer Engineering, or related field12+ years of experience in DFT engineering with complex SoC/ASIC products5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies5+ years in technical leadership or management rolesProven track record of multiple successful tape-outs with high-volume productionExperience taking multi-die products from design through production rampTechnical ExpertiseDeep expertise in DFT methodologies and industry standardsStrong background in 2.5D/3D packaging technologies:Silicon interposer-based designsTSV technology and testingChiplet architectures and die-to-die interfacesKnown Good Die (KGD) test strategiesCoWoS, EMIB, or similar advanced packaging platformsUnderstanding of JEDEC standards for multi-die testing (e.g., JESD229, JESD235)Experience with DFT EDA tools (Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, etc.)Strong understanding of ASIC design flow from RTL to GDSKnowledge of high-speed SerDes architectures and testing requirementsFamiliarity with ATE platforms (Advantest, Teradyne) and test program development for advanced packagesUnderstanding of production test economics and yield analysis for multi-die productsExperience with IEEE 1149.1, IEEE 1687 (IJTAG), and IEEE 1838 (3D-DFT) standardsLeadership & CommunicationProven ability to build, lead, and mentor high-performing engineering teamsExcellent communication skills with ability to influence across organizationsStrategic thinking with strong execution and problem-solving capabilitiesExperience managing projects with competing priorities and tight schedulesAbility to work effectively with external partners (OSATs, packaging vendors)Preferred QualificationsExperience with PCIe, CXL, or other high-speed serial protocolsBackground in SerDes architecture and testingExperience with HBM (High Bandwidth Memory) testing in 2.5D packagesKnowledge of chiplet-based system architectures (UCIe, BoW, AIB)Familiarity with 3D stacking technologies (face-to-face, face-to-back bonding)Experience with wafer-level testing and probe strategies for advanced packagesFamiliarity with functional safety requirements (ISO 26262) or automotive quality standardsExperience with machine learning approaches to test optimizationUnderstanding of PCIe/CXL link training, equalization, and state machinesPrior experience in networking or switch product developmentKnowledge of thermal and power integrity considerations in 3D packagesExperience with DTCO (Design-Technology Co-