DFT Design Engineer for ML Acceleration ASICs

Annapurna Labs (U.S.) Inc. in Austin, Texas, is seeking an ASIC DFT Design Engineer to design and optimize DFT architectures for advanced SoCs used in AWS data centers.

You will collaborate with block designers and PD teams, implement RTL in Verilog/SystemVerilog and push high-coverage test patterns for silicon at scale. This role requires a Bachelor's in Electrical/Communications Eng, 5+ years in DFT, experience with ATPG/JTAG/MBIST, and scripting.