Design Verification Engineer (VLSI/UVM)

Apple Inc. in Waltham, MA seeks a verification engineer to design and execute detailed test plans for high‑performance VLSI blocks. You will create verification environments with stimulus, checkers, and coverage, and run regression suites across IP and SoC levels.

You will use SystemVerilog and UVM to build testbenches, automate tasks with Python/Perl/Tcl, and leverage formal verification tools and industry-standard tools such as Cadence Xcelium, Verdi, Jasper Gold, and VManager.