A cutting-edge technology company in San Jose is seeking a Design Verification Engineer. The role demands expertise in UVM and SystemVerilog to ensure custom IPs are robust and silicon-ready. You will tackle complex verification challenges, collaborating closely with teams to validate performance across the hardware-software stack. The company offers generous benefits including medical coverage, housing subsidies, and daily meals, along with a competitive compensation range of $150K - $275K.
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Design Verification Engineer – Systolic Arrays & NoCs in san jose at Unknown Company
This position is listed as full time and onsite.