Apple Inc. is seeking a Design Verification Engineer in Santa Clara, CA to verify the functionality and performance of Apple’s premier SOCs.
You will own test plans, coverage, and testbenches, collaborating with design, micro-architecture, and software teams to ensure high quality designs. Minimum qualifications include a BS with 3+ years of experience and strong SystemVerilog/UVM expertise, plus Python/C/C++ and scripting skills.
#J-18808-LjbffrDesign Verification Engineer, SOC & Hardware, Stock Options in santa clara at Unknown Company
This position is listed as full time and onsite.