A leading technology company located in Cupertino is seeking a Design Verification Engineer who will be responsible for verifying the functionality and performance of SOCs. The role involves collaboration across various teams to ensure the highest quality in chip design, requiring knowledge of digital design fundamentals and programming languages. With a base pay range of $126,800 to $190,900, the position also offers comprehensive benefits including medical coverage, stock programs, and educational reimbursements.
#J-18808-Ljbffr
#J-18808-Ljbffr