A leading technology company in Los Angeles is seeking a skilled design verification engineer to ensure bug-free first silicon for its products. The successful candidate will be responsible for developing verification methodology, test plans, and environments. Required qualifications include a bachelor's degree and deep knowledge of SystemVerilog and UVM. Preferred candidates will have 3+ years experience and familiarity with verification methodologies, simulators, and serial protocols. Compensation ranges from $120,300 to $210,100 with various benefits.
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Design Verification Engineer — Silicon IP DV & Equity Options in los angeles at Unknown Company
This position is listed as full time and onsite.