Design Verification Engineer

Design Verification Engineer

Location: Santa Clara, CA

Duration: Long term

Experience: 8-15 Years

Key Responsibilities

• Strong understanding of SystemVerilog (SV) and UVM and good debugging skills.
• Understanding of AMBA protocols.
• Understand design specs and develop test plans based on functional and architectural requirements.
• Build UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC level testing.
• Develop directed and random test cases, perform coverage analysis, and close functional/code coverage.
• Debug simulation failures and work closely with RTL designers to resolve issues.
• Execute regression runs, analyze results, and contribute to continuous improvements.
• Integrate and run power‑aware simulations, low‑power checks, and work with UPF/CPF as needed.
• Collaborate with DFT/PD/RTL teams and post‑silicon validation to ensure design quality across domains.
• Document test environments, test plans, and results for internal and external reviews.