Design Verification Engineer

Design Verification Engineer, Principal

Santa Clara, CA - Onsite

Full Time

As a leading member of the Network Switching team you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. Your role may also include project management and leading a team of verification engineers on a project level.

Activities may include:

• Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.


• Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues.


• Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.


• Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.


• Unit and regression testing of software tools.

What We're Looking For

• BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).


• Proven track records of leading Design Verification implementation activity. Tape-out of complex SOC under tight schedule.


• In depth understanding and experience with System Verilog, UVM.


• In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.


• Experience with scripting language such as Python or Perl and EDA Verification tools.


• Experience with Object-Oriented Design and implementation.


• Good understanding of Linux O.S.


• Good programming skills desired, especially C++ and ARM assembly.


• Understanding of networking protocols, a plus.