- Verify the PCIe Gen6 subsystem using SystemVerilog/UVM.
- Develop verification plans, testbenches, test cases, assertions, and functional coverage.
- Verify LTSSM, Link Training, FLIT mode, Flow Control, Error Handling, Power Management, and PCIe protocol compliance.
- Integrate PCIe VIPs, execute regressions, debug failures, and drive coverage closure.
- Collaborate with RTL, Architecture, and Validation teams through verification signoff.
Required Skills
- Strong SystemVerilog/UVM expertise.
- Experience with PCIe VIPs, assertions (SVA), constrained-random verification, and coverage closure.
- Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).
- Good debugging and communication skills.