Design Verification Engineer | FPGA

FPGA Design Verification EngineerClient-Boeing IP layer-  VDartLocation: El Segundo, CA, onsite five days per weekEmployment Type: W-2 ContractDuration: 12 monthsCompensation:$70 per hourWork Authorization: U.S. citizenship requiredExperience: 5+ years in FPGA Design VerificationClearance: DoD Secret clearance preferredJob Description: Key Skills:FPGA Design VerificationSystemVerilog and UVM testbench developmentC test development and hardware/software integrationTest plan development, functional coverage, and coverage closureUniversal Verification Component (UVC) developmentFPGA verification from test planning through tape-outResponsibilitiesDevelop and maintain SystemVerilog/UVM testbenches, reusable Universal Verification Components (UVCs), and automated tests.Create verification plans covering FPGA functionality, interfaces, and hardware/software interactions.Develop and integrate C-based tests, APIs, and software build flows.Implement mailbox mechanisms and communication components supporting hardware/software verification.Collect and analyze functional and code coverage, identify gaps, and drive coverage closure.Debug test failures, document defects, and collaborate with design and firmware engineers to resolve issues.Work with verification, architecture, design, and firmware teams to define verification scope and review results.Improve verification environments to increase defect detection and test efficiency.Own verification deliverables, communicate risks, and escalate issues when appropriate.Mentor junior engineers and participate in technical reviews. Preferred Skills:SpaceWire ProtocolDDR4 Memory InterfacesSerDes ConnectivityConfiguration, Control, and Telemetry Systems