- Contribute to the verification of System IP, including coherent interconnects and caches
- Execute verification strategy, implement best practices, and support project goals in collaboration with global cross-functional teams
- Develop and maintain deep expertise in microarchitecture and design verification for coherent interconnect IPs
- Architect, develop, and maintain reusable verification environments and testbenches
- Support design excellence and thorough verification of key features
- Contribute to defining new verification methodologies and improving flows and productivity
- Collaborate with design, SoC, physical design, and performance verification teams to analyze and debug failures
Requirements
- 10+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 8+ years with a Master's Degree, or 6+ years with a Ph.D.
- 8+ years of professional experience in a design verification role building testbenches from scratch
- Strong background in design verification of coherent interconnects
- Proficiency in ARM protocols - CHI, AXI, ACElite, APB
- Strong coding skills in System Verilog, UVM
- Experience with Git version control, Unix/Perl scripting
- Formal verification skills will be a plus
Demonstrates extensive expertise in design verification, particularly for coherent interconnect IPs, with a strong focus on developing reusable verification environments and methodologies. Proficient in ARM protocols and coding in System Verilog and UVM, while collaborating effectively with cross-functional teams to ensure design excellence.
Highest-signal resume keywords
- Design Verification
- Coherent Interconnects
- System Verilog
- UVM
- ARM Protocols
Hard Skills
- Design Verification
- Testbench Development
- System Verilog
- UVM
- ARM Protocols
- Git Version Control
- Unix Scripting
- Perl Scripting
- Formal Verification
Soft Skills
- Collaboration
- Problem Solving
Industry Keywords
- Microarchitecture
- Verification Methodologies
- Interconnect IP
- SoC Design
- Performance Verification