Design Verification Engineer

In this role, you will be responsible for ensuring bug‑free first silicon for part of the SoC/IP and are encouraged to develop detailed test and coverage plans based on the micro‑architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will develop a verification environment, including all components such as stimulus, checkers, assertions, trackers and coverage. A mindset to break the design is highly desirable. Furthermore, you will learn to develop verification plans for all features, implement these plans, support design bring‑up, DV environment bring‑up, regression enabling and debug of test failures. You will also create block, IP and SoC‑level testbenches, track and report DV progress using a variety of metrics, including bugs and coverage. You will be expected to use LLM and related technologies to achieve efficient execution and improved quality.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Minimum Qualifications

• Minimum requirement of a bachelor's degree

Preferred Qualifications

• BS degree in technical subject area and a minimum 3 years relevant industry experience strongly preferred
• Strong knowledge of OOP, SystemVerilog and UVM
• Strong knowledge in developing scalable and portable testbenches
• Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate-level simulations
• Some working experience using LLMs for efficiency and quality
• Experience with power‑aware (UPF) or similar verification methodology
• Knowledge of a scripting language such as Python, Perl, or TCL
• Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
• Knowledge of formal verification methodology is a plus but not required
• Knowledge of emulation for verification technologies is a plus but not required

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