We're working with one of the most prestigious high‑frequency trading companies in the world to find a verification engineer to help verify their complex low‑latency FPGA systems.
You'l be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside pioneers in open‑source hardware tools.
Responsibilities
- Design and maintain robust testbenches and targeted tests using the organisation’s mixed open‑source and proprietary verification environment.
- Develop and own comprehensive verification plans, ensuring coverage goals and test strategies are clear and defensible.
- Identify and diagnose RTL issues quickly, working directly with designers to accelerate bring‑up and resolve design defects efficiently.
- Oversee and refine the test infrastructure, including management of test suites, CI pipelines, and the improvement of both internal and open‑source tooling.
Requirements
- Strong debugging and analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently.
- Proficiency in Python for building verification infrastructure, tooling, and automation - beyond simple scripts.
- Professional RTL functional verification experience for FPGA or ASIC designs.
- Hands‑on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis.