Locations
Austin, TX or Santa Clara, CA or Boston, MA - Onsite
Experience
Minimum 8+ years of experience
Preferred Experience
- Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes.
- Exposure to RTL design, software development, formal verification, or other related domains.
- Good understanding of computer organization/architecture.
- Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
Responsibilities
- Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design.
- Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
- Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
- Collaborate with architects, hardware engineers, and multiple IP development groups.
- Drive formal verification for the block and write formal properties and assertions to verify the design.
- Responsible for verification quality metrics like pass rates, code coverage and functional coverage.
Qualifications
- Bachelors or Masters degree in computer engineering/Electrical Engineering preferred