Design Verification Engineer

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Avanciers is seeking a highly skilled Design Verification Engineer to join our team for an exciting Fulltime project with one of our esteemed Fortune 500 clients, based in Sunnyvale CA // Austin TX Onsite

Location: Sunnyvale CA // Austin TX Onsite

Key Responsibilities:

• Strong understanding of SV and UVM and good debugging skills.
• Understanding of AMBA protocols.
• Understand design specs and develop test plans based on functional and architectural requirements
• Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
• Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
• Debug simulation failures and work closely with RTL designers to resolve issues
• Execute regression runs, analyze results, and contribute to continuous improvements
• Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
• Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
• Document test environments, test plans, and results for internal and external reviews

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering, Information Technology, and Consulting

• Industries

  IT Services and IT Consulting, Telecommunications, and Business Consulting and Services

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401(k)

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