Design Verification Engineer - AI ASIC IP UVM/SystemVerilog

Etched.ai, Inc. is looking for a Design Verification Engineer to join our Internal IP DV team in Austin, Texas. In this role, you will ensure the robustness and high performance of custom IPs by developing UVM/SystemVerilog testbenches and executing verification plans. Ideal candidates will have a strong background in UVM, digital design, and debugging skills. Benefits include medical coverage, wellness programs, and daily meals in the office. Expect to work closely with teams in both Austin and San Jose.
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