Design Verification Engineer: Accelerate ASIC/SoC Validation

MaximaTek seeks a detail-oriented Design Verification Engineer to manage ASIC/SoC verification workflows and testbench architecture, bridging RTL design teams, system architects, and EDA vendors. You will drive constrained random stimulus, regression scheduling, and functional coverage analyses, ensuring adherence to security standards and tape-out readiness.

Ideal candidates have 0–5 years in digital design verification, strong scripting/HDL skills, and excellent technical writing abilities,