Design Verification Architect – Networking SoC

AMD in Santa Clara is seeking a Design Verification Engineer to contribute to advanced data center networking technology. The ideal candidate should have strong expertise in SystemVerilog and UVM, with a focus on complex ASIC designs. Responsibilities include developing testbench architectures and ensuring verification closure on next-generation AMD products.

Join a fast-paced collaborative environment and drive innovation in data center solutions. A Bachelor’s Degree in Electrical/Computer Engineering is required, with a Master’s degree preferred.