As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. A ServiceNow-invested company, Prodapt has been recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider. Prodapt's ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. A "Great Place To Work Certified™" company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally. The team is looking for a Design-for-Test contractor to test and validate the next generation client chips preferable in San Diego, CA but open to San Jose, CA location as well. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets.
Experience with automation and scripting – Tcl/Perl/Python * Experience with RTL design – Verilog/system Verilog * Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)
5+ years relevant industrial DFT experience *Tech: Electronics and Communication Engineering (ECE), Electrical and Electronics Engineering (EEE), Electronics Engineering, or a related field. *
Design/Test Engineering Intern in san diego at Unknown Company
This position is listed as contract and onsite.