Intel Corporation in Arizona seeks a Defect Metrology Layer Owner to drive data-driven defect reduction in a high‑volume semiconductor environment. You will analyze complex yield data, collaborate with process engineers, and guide corrective actions to improve tool and process capability.
The role requires strong problem-solving, communication, and teamwork skills, with on-site presence in Phoenix. Preferred candidates may hold TS clearance and programming experience in JMP/JSL, Python, R, and
#J-18808-LjbffrDefect Metrology Lead - Semiconductor Yield & Analysis in phoenix at Unknown Company
This position is listed as full time and onsite.