DDRSS Validation Engineer (RTL + Silicon Debug)

Job Title: Validation EngineerWe are seeking a highly motivated validation engineer with strong debugging and firmware development skills to support next-generation SoC platforms. This role spans pre-silicon verification, emulation, and post-silicon validation, with a focus on deep debug in RTL/Verilog environments and hands-on silicon bring-up.The ideal candidate will bridge the gap between design, DV, and system validation by developing firmware in C and ensuring robust functionality across simulation, emulation, and silicon platforms.Key ResponsibilitiesDrive end-to-end validation of SoC subsystems (DDR, memory controller, cache, interconnect) across:RTL simulation (Verilog/SystemVerilog)Emulation platformsPost-silicon environmentsPerform deep debug of functional issues including:Root-causing failures in RTL simulations and testbenchesDebugging firmware-driven flowsAnalyzing silicon failures (timing, stability, performance)Develop and maintain production quality firmware in C to:Manage DDRSS IP sequences through init, frequency and power management.Enable bring-up and feature validationExercise system-level use casesSupport debug and characterizationValidate firmware across:RTL simulation environmentsEmulation systemsSilicon platformsCollaborate cross-functionally with:Design (RTL/architecture teams)DV teams (testbench and coverage alignment)System and silicon validation teamsDevelop tools, debug infrastructure, and automation to improve:Validation efficiencyData collection and analysisFailure triage and turnaround timeRequired Qualifications6–9 years of experience in SoC validation, design verification, or post-silicon validationStrong debug skills in Verilog/SystemVerilog simulation environmentsExperience with firmware development in C for embedded systemsHands-on experience with silicon bring-up, debug, and validationExperience debugging across multiple platforms (simulation, emulation, silicon)Solid understanding of:Computer architecture and SoC subsystemsMemory systems (DDR, cache, interconnect)Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Pay range and Other Compensation & Benefits :$140,000.00 - $210,000.00