DDR PHY Design Engineer — RTL, Timing & Silicon Bring-Up

Apple Inc. in Austin, TX is seeking a results-oriented DDR Design Engineer to join the DDR PHY design team.

You will contribute across the full cycle—from concept study and architecture definition to synthesis, verification, silicon bring-up and characterization. You will provide RTL in Verilog/SystemVerilog, including assertions, and write detailed design specs and test plans in collaboration with architecture, circuit and verification engineers.