Data Fabric Verification Engineer | SystemVerilog & Formal

iFlow Inc. is looking for a Design Verification Engineer located in Sunnyvale, California. This long-term position requires expertise in System Verilog and a background in designing verification environments. The ideal candidate will have at least 5 years of experience and a strong understanding of RTL design and formal verification tools.

Responsibilities include writing test sequences, coordinating with engineers for logic design verification, and ensuring verification quality metrics are met. A Bachelor's or Master's degree in Computer or Electrical Engineering is preferred.