Google is hiring for a senior block-level physical design engineer to develop custom silicon powering its products. You will work on high-performance, low-power architectures, collaborating with RTL, architecture, and DFT teams to meet tight parity and timing goals.
The role emphasizes signoff discipline, STA, physical verification, and QoR improvements to deliver efficientcompute blocks, with input on preferred working location from Austin, TX or Mountain View, CA.
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